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MOTOROLA
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SEMICONDUCTOR
TECHNICAL DATA
MC68LK332
Technical Supplement
16.78 MHz Electrical Characteristics
Devices in the 68300 Modular Microcontroller Family are built up from a selection of standard functional modules. The MC68LK332 incorporates a central processing unit (CPU32), a system integration module (SIM), a queued serial module (QSM), a time processor unit (TPU), and a 2 K-byte static RAM module with TPU emulation capability (TPURAM). The functionality of the MC68LK332 is enhanced from the MC68L332 to include an operational PLL. This publication contains a new electrical characteristics appendix for the MC68LK332 to be used in conjunction with the MC68332 User's Manual (MC68332UM/AD).
PRELIMINARY
(c) MOTOROLA INC, 1997
LIST OF ILLUSTRATIONS
Figure Title Page
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLKOUT Output Timing Diagram ..............................................................................................12 External Clock Input Timing Diagram ........................................................................................12 ECLK Output Timing Diagram ...................................................................................................12 Read Cycle Timing Diagram .....................................................................................................13 Write Cycle Timing Diagram ......................................................................................................14 Fast Termination Read Cycle Timing Diagram .........................................................................15 Fast Termination Write Cycle Timing Diagram ..........................................................................16 Bus Arbitration Timing Diagram -- Active Bus Case ................................................................17 Bus Arbitration Timing Diagram -- Idle Bus Case ....................................................................18 Show Cycle Timing Diagram .....................................................................................................19 Chip-Select Timing Diagram .....................................................................................................20 Reset and Mode Select Timing Diagram ...................................................................................20 BDM Serial Communication Timing Diagram ............................................................................21 BDM Freeze Assertion Timing Diagram ....................................................................................21 ECLK Timing Diagram ...............................................................................................................23 QSPI Timing -- Master, CPHA = 0 ...........................................................................................25 QSPI Timing -- Master, CPHA = 1 ...........................................................................................25 QSPI Timing -- Slave, CPHA = 0 .............................................................................................26 QSPI Timing -- Slave, CPHA = 1 .............................................................................................26 TPU Timing Diagram .................................................................................................................27
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MC68LK332 MC68LK332EC16/D
LIST OF TABLES
Table Title Page
1 2 3 4 5 6 7 8 9 10
Maximum Ratings ........................................................................................................................4 MC68LK332 Typical Ratings .......................................................................................................5 Thermal Characteristics ..............................................................................................................5 Clock Control Timing ...................................................................................................................6 16.78 MHz DC Characteristics ....................................................................................................7 16.78 MHz AC Timing .................................................................................................................9 Background Debugging Mode Timing .......................................................................................21 ECLK Bus Timing ......................................................................................................................22 QSPI Timing ..............................................................................................................................24 Time Processor Unit Timing ......................................................................................................27
MC68LK332 MC68LK332EC16/D
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Table 1 Maximum Ratings
Num 1 2 3 Rating Supply Voltage1, 2, 3 Input Voltage 1, 2, 3, 4, 5, 7 Instantaneous Maximum Current Single Pin Limit (all pins)1, 3, 5, 6 Operating Maximum Current Digital Input Disruptive Current3, 5, 6, 7, 8 VNEGCLMAP - 0.3 V
VPOSCLAMP VDD + 0.3
Symbol VDD VIN ID
Value - 0.3 to + 6.5 - 0.3 to + 6.5 25
Unit V V mA
4
Iid
- 500 to 500
A
5 6
Operating Temperature Range C Suffix Storage Temperature Range
TA Tstg
TL to TH - 40 to 85 - 55 to 150
C C
NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. This parameter is periodically sampled rather than 100% tested. 4. All pins except TSC. 5. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current. 7. All functional non-supply pins are internally clamped to VSS. All functional pins except EXTAL and XFC are internally clamped to VDD. 8. Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.
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MC68LK332 MC68LK332EC16/D
Table 2 MC68LK332 Typical Ratings
Num 1 2 Supply Voltage Operating Temperature VDD Supply Current RUN LPSTOP, VCO off LPSTOP, External clock, max fsys Clock Synthesizer Operating Voltage VDDSYN Supply Current VCO on, maximum fsys External Clock, maximum fsys LPSTOP, VCO off VDD powered down RAM Standby Current Normal RAM operation Standby operation Power Dissipation Rating Symbol VDD TA Value 3.3 25 45 125 1.0 3.3 1.0 2.0 100 50 3.0 10 148.0 Unit V C mA A mA V mA mA A A A A mW
3
IDD
4
VDDSYN
5
IDDSYN
6 7
ISB PD
Table 3 Thermal Characteristics
Num 1 Rating Symbol Value 38 49 Unit C/W Thermal Resistance Plastic 132-Pin Surface Mount JA Plastic 144-Pin Surface Mount The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JA ) (1) where: = Ambient Temperature, C TA JA = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O PD PINT = IDD x VDD, Watts -- Chip Internal Power PI/O = Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K / ( T J + 273C ) (2) Solving equations 1 and 2 for K gives: K = P D x ( T A + 273C ) + JA x P D
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
MC68LK332 MC68CK331EC16/D
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Table 4 Clock Control Timing (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)
Num 1 2 Characteristic PLL Reference Frequency Range System Frequency1 On-Chip PLL System Frequency External Clock Operation PLL Lock Time2, 3, 4, 5 VCO Frequency6 CLKOUT Jitter2, 3, 4, 7 Short term (5 s interval) Long term (500 s interval) Symbol fref fsys tlpll fVCO Jclk Min 20 4(fref) dc -- -- Max 50 16.78 16.78 20 2 (fsys max) 1.0 0.5 Unit kHz MHz
3 4
ms MHz
5
-1.0 -0.5
%
NOTES: 1. All internal registers retain data at 0 Hz. 2. This parameter is periodically sampled rather than 100% tested. 3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total external resistance from the XFC pin due to external leakage must be greater than 15 M to guarantee this specification. Filter network geometry can vary depending upon operating environment. 4. Proper layout procedures must be followed to achieve specifications. 5. Assumes that stable VDDSYN is applied, and that the crystal oscillator is stable. Lock time is measured from the time VDD and VDDSYN are valid until RESET is released. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 6. Internal VCO frequency (fVCO) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a divideby-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and fsys = fVCO / 4. When X = 1, the divider is disabled, and fsys = fVCO / 2. X must equal one when operating at maximum specified fsys. 7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSS and variation in crystal oscillator frequency increase the Jclk percentage for a given interval. When jitter is a critical constraint on control system operation, this parameter should be measured during functional testing of the final system.
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MC68LK332 MC68LK332EC16/D
Table 5 16.78 MHz DC Characteristics (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)
Num 1 2 3 4 Input High Voltage Input Low Voltage Input Hysteresis1 Characteristic Symbol VIH VIL VHYS Iin Min 0.7 (VDD) VSS - 0.3 0.5 Max VDD + 0.3 0.2 (VDD) -- Unit V V V A A V
Input Leakage Current 2 Vin = VDD or VSS Input-only pins High Impedance (Off-State) Leakage Current2 Vin = VDD or VSS All input/output and output pins CMOS Output High Voltage2, 3 IOH = -10.0 A Group 1, 2, 4 input/output and output pins CMOS Output Low Voltage2 IOL = 10.0 A Group 1, 2, 4 input/output and output pins TTL Compatible Output High Voltage2, 3 IOH = -0.4 mA Group 1, 2, 4 input/output and output pins TTL Compatible Output Low Voltage2 IOL = 0.8 mA Group 1 I/O pins, CLKOUT, FREEZE/QUOT, IPIPE/DSO IOL = 2.6 mA Group 2 and Group 4 I/O pins, CSBOOT, BG/CS1 IOL = 6.0 mA Group 3 Three State Control Input High Voltage Data Bus Mode Select Pull-up Current 4 Vin = VIL Vin = VIH VDD Supply Current5 Run LPSTOP, external clock input frequency = max fsys Run, emulation mode LPSTOP, crystal reference, VCO off (STSIM = 0) Clock Synthesizer Operating Voltage VDDSYN Supply Current External clock, maximum fsys Crystal reference, VCO on, maximum fsys LPSTOP, crystal reference, VCO off, (STSIM = 0) VDD powered down RAM Standby Voltage Specified VDD applied VDD = VSS
-2.5
2.5
5
IOZ
-2.5 VDD -0.2
2.5 --
6
VOH
7
VOL
--
0.2
V
8
VOH
VDD -0.5
--
V
9
VOL
-- -- --
0.4 0.4 0.4 9.1
V
10
VIHTSC IMSP
2.4 (VDD) -- -8
V A
11
-95 --
12
IDD
-- -- -- -- 3.0
56 2 59 350 3.6
mA mA mA A V
13
VDDSYN
14
IDDSYN
-- -- -- --
3 1 150 100
mA mA A A
15
VSB
0.0 2.7
VDD 3.6
V
MC68LK332 MC68CK331EC16/D
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Table 5 16.78 MHz DC Characteristics (Continued) (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)
Num RAM Standby Current6, 7 Normal RAM operation 16 Transient condition Standby operation 17 Power Dissipation8 Input Capacitance2, 9 All input-only pins All input/output pins Load Capacitance2 Group 1 I/O Pins, CLKOUT, FREEZE/QUOT, IPIPE/DSO Group 2 I/O Pins and CSBOOT, BG/CS1 Group 3 I/O Pins Group 4 I/O Pins Characteristic VDD > VSB - 0.5 V Symbol Min Max Unit
VSB - 0.5 V VDD VSS + 0.5 V VDD < VSS + 0.5 V
ISB
-- -- -- -- -- --
10 3 50 212 10 20
A mA A mW pF
PD Cin
18
19
CL
-- -- -- --
90 100 100 100
pF
NOTES: 1. Applies to: QSM pins IRQ[7:1], RESET, EXTAL, TSC, RMC, BKPT/DSCLK, IFETCH/DSI 2. Input-Only Pins: TSC, BKPT/DSCLK, RXD Output-Only Pins: CSBOOT, BG/CS1, CLKOUT, FREEZE/QUOT, IPIPE/DSO Input/Output Pins: Group 1: DATA[15:0], IFETCH/DSI Group 2: ADDR[23:19]/CS[10:6], FC[2:0]/CS[5:3], DSACK[1:0], AVEC, RMC, DS, AS, SIZ[1:0] IRQ[7:1], MODCLK, ADDR[18:0], R/W, BERR, BR/CS0, BGACK/CS2, PCS[3:1], PCS0/SS, TXD Group 3: HALT, RESET Group 4: MISO, MOSI, SCK 3. Does not apply to HALT and RESET because they are open drain pins. Does not apply to Port QS[7:0] (TXD, PCS[3:1], PCS0/SS, SCK, MOSI, MISO) in wired-OR mode. 4. Current measured at maximum system clock frequency. 5. Total operating current is the sum of the appropriate VDD supply and VDDSYN supply current. 6. When VSB is more than 0.3V greater than VDD, current flows between the VSTBY and VDD pins, which causes standby current to increase toward the maximum condition specification. System noise on the VDD and VSTBY pin can contribute to this condition. 7. The SRAM module will not switch into standby mode as long as VSB does not exceed VDD by more than 0.5 volts. The SRAM array cannot be accessed while the module is in standby mode. 8. Power dissipation measured at specified system clock frequency, all modules active. Power dissipation can be calculated using the expression: PD = 3.6V (IDDSYN + IDD) IDD includes supply currents for all device modules powered by VDD pins 9. Input capacitance is periodically sampled rather than 100% tested.
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MC68LK332 MC68LK332EC16/D
Table 6 16.78 MHz AC Timing (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH1
Num F1 1 1A 1B 2, 3 Frequency of Operation Clock Period ECLK Period External Clock Input Period2 Clock Pulse Width Characteristic Symbol f tcyc tEcyc tXcyc tCW tECW tXCHL tCrf trf tXCrf tCHAV tCHAZx tCHAZn tCLSA tSTSA tCLIA tAVSA tCLSN tCLIN tSNAI tSWA tSWAW tSWDW tSN tCHSZ tSNRN tCHRH tCHRL tRAAA tRASA tCHDO Min DC 59.6 476 59.6 24 236 29.8 -- -- -- 0 0 0 0 -15 2 15 2 2 15 100 45 40 40 -- 15 0 0 15 70 -- Max Unit
16.78 MHz -- -- -- -- -- -- 7 8 4 29 59 -- 25 15 22 -- 29 29 -- -- -- -- -- 59 -- 29 29 -- -- 29 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2A, 3A ECLK Pulse Width 2B, 3B External Clock Input High/Low Time2 4, 5 CLKOUT Rise and Fall Time
4A, 5A Rise and Fall Time (All outputs except CLKOUT) 4B, 5B External Clock Input Rise and Fall Time 6 7 8 9 9A 9C 11 12 12A 13 14 14A 14B 15 16 17 18 20 21 22 23 Clock High to ADDR, FC, RMC, SIZ Valid Clock High to ADDR, Data, FC, RMC,SIZ High Impedance Clock High to ADDR, FC, RMC, SIZ Invalid Clock Low to AS, DS, CS Asserted AS to DS or CS Asserted (Read)3 Clock Low to IFETCH, IPIPE Asserted ADDR, FC, RMC, SIZ Valid to AS, CS, (and DS Read) Asserted Clock Low to AS, DS, CS Negated Clock Low to IFETCH, IPIPE Negated AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) AS, CS (and DS Read) Width Asserted DS, CS Width Asserted (Write) AS, CS (and DS Read) Width Asserted (Fast Cycle) AS, DS, CS Width Negated4 Clock High to AS, DS, R/W High Impedance AS, DS, CS Negated to R/W High Clock High to R/W High Clock High to R/W Low R/W High to AS, CS Asserted R/W Low to DS, CS Asserted (Write) Clock High to Data Out Valid
MC68LK332 MC68CK331EC16/D
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Table 6 16.78 MHz AC Timing (Continued) (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH1
Num 24 25 26 27 27A 28 29 29A 30 30A 31 33 35 37 39 39A 46 46A 47A 47B 48 53 54 55 70 71 72 73 74 75 76 Characteristic Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) DS, CS Negated to Data Out Invalid (Data Out Hold) Data Out Valid to DS, CS Asserted (Write) Data In Valid to Clock Low (Data Setup) Late BERR, HALT Asserted to Clock Low (Setup Time) AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated DS, CS Negated to Data In Invalid (Data In Hold)5 DS, CS Negated to Data In High Impedance5, 6 CLKOUT Low to Data In Invalid (Fast Cycle Hold)5 CLKOUT Low to Data In High Impedance5 DSACK[1:0] Asserted to Data In Valid7 Clock Low to BG Asserted/Negated BR Asserted to BG Asserted (RMC not Asserted)8 BGACK Asserted to BG Negated BG Width Negated BG Width Asserted R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Write or Read Cycle) Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT Asynchronous Input Hold Time DSACK[1:0] Asserted to BERR, HALT Data Out Hold from Clock High Clock High to Data Out High Impedance R/W Asserted to Data Bus Impedance Change Clock Low to Data Bus Driven (Show Cycle) Data Setup Time to Clock Low (Show Cycle) Data Hold from Clock Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time Mode Select Setup Time Mode Select Hold Time Asserted9 Symbol tDVASN tSNDOI tDVSA tDICL tBELCL tSNDN tSNDI tSHDI tCLDI tCLDH tDADI tCLBAN tBRAGA tGAGN tGH tGA tRWA tRWAS tAIST tAIHT tDABA tDOCH tCHDH tRADC tSCLDD tSCLDS tSCLDH tBKST tBKHT tMSS tMSH Min 15 15 15 5 20 0 0 -- 10 -- -- -- 1 1 2 1 150 90 5 15 -- 0 -- 40 0 15 10 15 10 20 0 Max -- -- -- -- -- 80 -- 55 -- 90 50 29 -- 2 -- -- -- -- -- -- 30 -- 28 -- 29 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns tcyc tcyc tcyc tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns tcyc ns
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MC68LK332 MC68LK332EC16/D
Table 6 16.78 MHz AC Timing (Continued) (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH1
Num 77 78 RESET Assertion Time10 RESET Rise Time11, 12 Characteristic Symbol tRSTA tRSTR Min 4 -- Max -- 10 Unit tcyc tcyc
NOTES: 1. All AC timing is shown with respect to 2.0 V to 0.8 V levels unless otherwise noted. 2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% - external clock input duty cycle tolerance). 3. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside the limits shown in specification 9. 4. If multiple chip-selects are used, CS width negated (specification 15) applies to the time from the negation of a heavily loaded chip-select to the assertion of a lightly loaded chip select. The CS width negated specification between multiple chip-selects does not apply to chip selects being used for synchronous ECLK cycles. 5. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads. The user is free to use either hold time. 6. Maximum value is equal to (tcyc / 2) + 25 ns. 7. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle. 8. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of the current operand transfer are complete. 9. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification 47A). 10. After external RESET negation is detected, a short transition period (approximately 2) tcyc elapses, then the SIM drives RESET low for 512 tcyc. 11. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles. 12. External logic must pull RESET high during this period in order for normal MCU operation to begin.
MC68LK332 MC68CK331EC16/D
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1 4 CLKOUT 2 3
5
68300 CLKOUT TIM
Figure 1 CLKOUT Output Timing Diagram
1B 4B EXTAL 2B 3B
5B
NOTE: PULSE WIDTH SHOWN WITH RESPECT TO 50% VDD.
68300 EXT CLK INPUT TIM
Figure 2 External Clock Input Timing Diagram
1A 4A ECLK 2A 3A
5A
68300 ECLK OUTPUT TIM
Figure 3 ECLK Output Timing Diagram
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MC68LK332 MC68LK332EC16/D
S0 CLKOUT
S1
S2
S3
S4
S5
6 ADDR[23:20]
8
FC[2:0]
SIZ[1:0] 11 AS 9 DS 9A CS 18 R/W 46 21 20 12 13 14 15
DSACK0 47A DSACK1 31 DATA[15:0] 27 29A BERR 48 HALT 9C 12A 27A 29 28
12A
IFETCH 73 BKPT 47A ASYNCHRONOUS INPUTS 47B 74
68300 RD CYC TIM
Figure 4 Read Cycle Timing Diagram
MC68LK332 MC68CK331EC16/D
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S0 CLKOUT 6 ADDR[23:20]
S1
S2
S3
S4
S5
8
FC[2:0]
SIZ[1:0] 11 AS 9 DS 21 9 CS 20 R/W 46 DSACK0 47A DSACK1 55 DATA[15:0] 23 BERR 48 27A HALT 74 73 BKPT 26 54 53 25 28 22 14A 17 12 14 15
13
68300 WR CYC TIM
Figure 5 Write Cycle Timing Diagram
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MC68LK332 MC68LK332EC16/D
S0 CLKOUT 6 ADDR[23:0]
S1
S4
S5
S0
8
FC[2:0]
SIZ[1:0] 14B AS 9 DS 12
CS 20 18 R/W 46A
27
30 30A
DATA[15:0] 73 29A 29
BKPT 74
68300 FAST RD CYC TIM
Figure 6 Fast Termination Read Cycle Timing Diagram
MC68LK332 MC68CK331EC16/D
MOTOROLA 15
S0 CLKOUT 6 ADDR[23:0]
S1
S4
S5
S0
8
FC[2:0]
SIZ[1:0] 14B AS 9 DS 12
CS 20 R/W 23 DATA[15:0] 73 25 24 18 46A
BKPT 74
68300 FAST WR CYC TIM
Figure 7 Fast Termination Write Cycle Timing Diagram
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MC68LK332 MC68LK332EC16/D
S0 CLKOUT
S1
S2
S3
S4
S5
S98
A5
A5
A2
ADDR[23:0] 7 DATA[15:0]
AS 16
DS
R/W
DSACK0
DSACK1 47A BR 35 BG 33 33 BGACK 37 39A
68300 BUS ARB TIM
Figure 8 Bus Arbitration Timing Diagram -- Active Bus Case
MC68LK332 MC68CK331EC16/D
MOTOROLA 17
A0 CLKOUT
A5
A5
A2
A3
A0
ADDR[23:0]
DATA[15:0]
AS 47A 47A
BR 35 BG 33 33 47A 37
BGACK
68300 BUS ARB TIM IDLE
Figure 9 Bus Arbitration Timing Diagram -- Idle Bus Case
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MC68LK332 MC68LK332EC16/D
S0 CLKOUT 6 ADDR[23:0] 18 R/W 20 AS
S41
S42
S43
S0
S1
S2
8
9
12 15
DS 71 70 DATA[15:0] 73 74 BKPT SHOW CYCLE START OF EXTERNAL CYCLE 72
NOTE: SHOW CYCLES CAN STRETCH DURING CLOCK PHASE S42 WHEN BUS ACCESSES TAKE LONGER THAN TWO CYCLES DUE TO IMB MODULE WAIT-STATE INSERTION.
68300 SHW CYC TIM
Figure 10 Show Cycle Timing Diagram
MC68LK332 MC68CK331EC16/D
MOTOROLA 19
S0 CLKOUT 6 ADDR[23:0]
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
6
8
FC[2:0]
SIZ[1:0] 11 AS 9 DS 21 CS 18 R/W 46 29 DATA[15:0] 27 29A 23 53 54 55 25 20 46 14A 18 12 9 9 14 11 14 13
15
17 21 12
17
68300 CHIP SEL TIM
Figure 11 Chip-Select Timing Diagram
77 RESET 75
78
DATA[15:0] 76
68300 RST/MODE SEL TIM
Figure 12 Reset and Mode Select Timing Diagram
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MC68LK332 MC68LK332EC16/D
Table 7 Background Debugging Mode Timing (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1
Num B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 DSI Input Setup Time DSI Input Hold Time DSCLK Setup Time DSCLK Hold Time DSO Delay Time DSCLK Cycle Time CLKOUT Low to FREEZE Asserted/Negated CLKOUT High to IFETCH High Impedance CLKOUT High to IFETCH Valid DSCLK Low Time Characteristic Symbol tDSISU tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZAN tIPZ tIP tDSCLO Min 15 10 15 10 -- 2 -- -- -- 1 Max -- -- -- -- 25 -- 50 50 50 -- Unit ns ns ns ns ns tcyc ns ns ns tcyc
NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
CLKOUT
FREEZE B3 B2 BKPT/DSCLK B9 B5 B1 B0 IFETCH/DSI
B4 IPIPE/DSO
68300 BKGD DBM SER COM TIM
Figure 13 BDM Serial Communication Timing Diagram
CLKOUT
B6 FREEZE B7 IFETCH/DSI B8
68300 BDM FRZ TIM
B6
Figure 14 BDM Freeze Assertion Timing Diagram
MC68LK332 MC68CK331EC16/D
MOTOROLA 21
Table 8 ECLK Bus Timing (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH)1
Num E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 ECLK Low to Address Characteristic Valid2 Symbol tEAD tEAH tECSD tECSH tECSN tEDSR tEDHR tEDHZ tECDH tECDZ tEDDW tEDHW tEACC tEACS tEAS Min -- 15 -- 15 30 30 5 -- 0 -- -- 15 386 296 1/2 Max 60 -- 150 -- -- -- -- 60 -- 1 2 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns tcyc tcyc ns ns ns tcyc
ECLK Low to Address Hold ECLK Low to CS Valid (CS Delay) ECLK Low to CS Hold CS Negated Width Read Data Setup Time Read Data Hold Time ECLK Low to Data High Impedance CS Negated to Data Hold (Read) CS Negated to Data High Impedance ECLK Low to Data Valid (Write) ECLK Low to Data Hold (Write) Address Access Time (Read)3
Chip-Select Access Time (Read)4 Address Setup Time
NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. When previous bus cycle is not an ECLK cycle, the address may be valid before ECLK goes low. 3. Address access time = tEcyc - tEAD - tEDSR. 4. Chip select access time = tEcyc - tECSD - tEDSR.
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MC68LK332 MC68LK332EC16/D
CLKOUT 2A ECLK 1A 3A
R/W E1 ADDR[23:0] E3 CS E15 E13 DATA[15:0] READ E7 E8 E11 DATA[15:0] WRITE E12
68300 E CYCLE TIM
E2
E14 E6
E4
E5
E9 WRITE
E10
Figure 15 ECLK Timing Diagram
MC68LK332 MC68CK331EC16/D
MOTOROLA 23
Table 9 QSPI Timing (VDD and VDDSYN = 3.0 to 3.6 Vdc, VSS = 0 Vdc, TA = TL to TH, 100 pF load on all QSPI pins)1
Num 1 Function Operating Frequency Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave2 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (after SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input Output Fall Time Input Output Symbol fop Min DC DC 4 4 2 2 -- 2 2 tcyc - 60 2 tcyc - n 17 13 30 20 0 20 -- -- -- -- 0 0 -- -- -- -- Max 1/4 1/4 510 -- 128 -- 1/2 -- 255 tcyc -- 8192 -- -- -- -- -- 1 2 50 50 -- -- 2 30 2 30 Unit fsys fsys tcyc tcyc tcyc tcyc SCK tcyc ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns ns ns ns s ns s ns
2
tqcyc
3
tlead
4
tlag
5
tsw
6
ttd
7
tsu
8 9 10 11
thi ta tdis tv
12
tho
13
tri tro tfi tfo
14
NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 2. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
MOTOROLA 24
MC68LK332 MC68LK332EC16/D
3 PCS[3:0] OUTPUT 13 12 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 6 7 MISO INPUT MSB IN DATA LSB IN 4 12 13 1 5
2
MSB IN
11 MOSI OUTPUT
10 DATA LSB OUT PORT DATA 12 MSB OUT
PD 13
MSB OUT
68300 QSPI MAST CPHA0
Figure 16 QSPI Timing -- Master, CPHA = 0
3 PCS[3:0] OUTPUT 13 1 SCK CPOL=0 OUTPUT 4 SCK CPOL=1 OUTPUT 4 12 13 6 MISO INPUT MSB IN DATA LSB IN 1 7 12 5
2
MSB
11 MOSI OUTPUT
10 DATA LSB OUT PORT DATA 12 MSB
PORT DATA 13
MSB OUT
68300 QSPI MAST CPHA1
Figure 17 QSPI Timing -- Master, CPHA = 1
MC68LK332 MC68CK331EC16/D
MOTOROLA 25
3 SS INPUT 13 12 SCK CPOL=0 INPUT 4 SCK CPOL=1 INPUT 4 8 MISO OUTPUT MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 11 DATA 12 13 10 LSB OUT 11 9 PD 13 1 5
2
MSB OUT
MSB IN
68300 QSPI SLV CPHA0
Figure 18 QSPI Timing -- Slave, CPHA = 0
SS INPUT 5 1 4 SCK CPOL=0 INPUT 2 SCK CPOL=1 INPUT 12 10 8 MISO OUTPUT PD MSB OUT 7 6 MOSI INPUT MSB IN DATA LSB IN 10 DATA 13 11 SLAVE LSB OUT 12 9 4 3 12 13
PD
68300 QSPI SLV CPHA1
Figure 19 QSPI Timing -- Slave, CPHA = 1
MOTOROLA 26
MC68LK332 MC68LK332EC16/D
Table 10 Time Processor Unit Timing (VDD and VDDA = 3.0 to 3.6Vdc, VSS = 0 Vdc, TA = TL to TH)1
Num 1 2 3 Parameter CLKOUT High to TPU Output Channel TPU Input Channel Pulse Width Valid2, 3, 4 Symbol tCHTOV tCHTOH tTIPW Min 2 0 4 Max 23 20 -- Unit ns ns tcyc
CLKOUT High to TPU Output Channel Hold
NOTES: 1. AC Timing is shown with respect to 20% VDD and 70% VDD levels. 2. Timing not valid for external T2CLK input. 3. Maximum load capacitance for CLKOUT pin is 90 pF. 4. Maximum load capacitance for TPU output pins is 100 pF.
CLKOUT 1 TPU OUTPUT 2
TPU INPUT
3
TPU I/O TIM
Figure 20 TPU Timing Diagram
MC68LK332 MC68CK331EC16/D
MOTOROLA 27
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